2784 search results - page 33 / 557 » Instruction Level Parallelism |
DATE
2010
IEEE
14 years 3 months ago
2010
IEEE
—In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communicati...
SC
1992
ACM
14 years 1 months ago
1992
ACM
Exploiting parallelism at both the multiprocessor level and the instruction level is an e ective means for supercomputers to achieve high-performance. The amount of instruction-le...
ASPDAC
2004
ACM
14 years 3 months ago
2004
ACM
— The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting their special architecture features. Beside the ...
MICRO
1993
IEEE
14 years 2 months ago
1993
IEEE
Compiler-controlled speculative execution has been shown to be e ective in increasing the availableinstruction level parallelism ILP found in non-numeric programs. An importantpr...
JSA
2000
13 years 9 months ago
2000
In this article, the problem of finding a tight estimate on the worst-case execution time (WCET) of a real-time program is addressed. The analysis is focused on straight-line code...