2784 search results - page 45 / 557 » Instruction Level Parallelism |
ISSS
2002
IEEE
14 years 2 months ago
2002
IEEE
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
MICRO
1995
IEEE
14 years 1 months ago
1995
IEEE
Instruction Level Parallelism (ILP) speedups of an order-of-magnitude or greater may be possible using the techniques described herein. Traditional speculative code execution is t...
IPPS
2006
IEEE
14 years 4 months ago
2006
IEEE
With the advent of chip-multiprocessors (CMPs), Thread-Level Speculation (TLS) remains a promising technique for exploiting this highly multithreaded hardware to improve the perfo...
IEEEPACT
2000
IEEE
14 years 2 months ago
2000
IEEE
Modern computers have taken advantage of the instruction-level parallelism (ILP) available in programs with advances in both architecture and compiler design. Unfortunately, large...
HPCA
2001
IEEE
14 years 10 months ago
2001
IEEE
The performance of out-of-order processors increases with the instruction window size. In conventional processors, the effective instruction window cannot be larger than the issue...