2784 search results - page 53 / 557 » Instruction Level Parallelism |
VEE
2006
ACM
14 years 3 months ago
2006
ACM
We present Vector LLVA, a virtual instruction set architecture (VISA) that exposes extensive static information about vector parallelism while avoiding the use of hardware-speciļ¬...
IEEEPACT
2000
IEEE
14 years 2 months ago
2000
IEEE
Recent digital signal processors (DSPs) show a homogeneous VLIW-like data path architecture, which allows C compilers to generate efļ¬cient code. However, still some special rest...
SBCCI
2006
ACM
14 years 3 months ago
2006
ACM
The growing complexity and production cost of processor-based systems have imposed big constraints in SoC design of new systems. GPPs and ASICs are unable to fit the tight perform...
ISCAPDCS
2007
13 years 11 months ago
2007
ā Next generation multimedia mobile phones that use the high bandwidth 3G cellular radio network consume more power. Multimedia algorithms such as speech, video transcodecs have ...
HPCA
2003
IEEE
14 years 10 months ago
2003
IEEE
Inherent within complex instruction set architectures such as x86 are inefficiencies that do not exist in a simpler ISAs. Modern x86 implementations decode instructions into one o...