2784 search results - page 55 / 557 » Instruction Level Parallelism |
IPPS
2003
IEEE
14 years 3 months ago
2003
IEEE
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
FMICS
2006
Springer
14 years 1 months ago
2006
Springer
Abstract. The design flow of systems-on-a-chip (SoCs) identifies several abstraction levels higher than the Register-Transfer-Level that constitutes the input of the synthesis tool...
EUROPAR
2010
Springer
13 years 11 months ago
2010
Springer
Manual parallelization of programs is known to be difficult and error-prone, and there are currently few ways to measure the amount of potential parallelism in the original sequent...
SIGMOD
2002
ACM
14 years 10 months ago
2002
ACM
Modern CPUs have instructions that allow basic operations to be performed on several data elements in parallel. These instructions are called SIMD instructions, since they apply a...
HICSS
1997
IEEE
14 years 2 months ago
1997
IEEE
The SB-PRAM is a massively parallel, uniform memory access (UMA) shared memory computer. The main ideas of the design are multithreading on instruction level, hashing of the addre...