Sciweavers

2784 search results - page 68 / 557
» Instruction Level Parallelism
Sort
View
DATE
2000
IEEE
86views Hardware» more  DATE 2000»
14 years 2 months ago
A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level
Simulation is still one of the most important subtasks when designing a VLSI circuit. However, more and more elements on a chip increase simulation runtimes. Especially on transis...
Norbert Fröhlich, Volker Gloeckel, Josef Flei...
IPPS
2007
IEEE
14 years 4 months ago
A Multi-Level Parallel Implementation of a Program for Finding Frequent Patterns in a Large Sparse Graph
Graphs capture the essential elements of many problems broadly defined as searching or categorizing. With the rapid increase of data volumes from sensors, many application discipl...
Steve Reinhardt, George Karypis
ISORC
2007
IEEE
14 years 4 months ago
Time-Predictable Task Preemption for Real-Time Systems with Direct-Mapped Instruction Cache
Modern processors used in embedded systems are becoming increasingly powerful, having features like caches and pipelines to speedup execution. While execution speed of embedded so...
Raimund Kirner, Peter P. Puschner
NAACL
2010
13 years 7 months ago
Extracting Parallel Sentences from Comparable Corpora using Document Level Alignment
The quality of a statistical machine translation (SMT) system is heavily dependent upon the amount of parallel sentences used in training. In recent years, there have been several...
Jason R. Smith, Chris Quirk, Kristina Toutanova
CASES
2005
ACM
13 years 12 months ago
Software-directed power-aware interconnection networks
Interconnection networks have been deployed as the communication fabric in a wide range of parallel computer systems. With recent technological trends allowing growing quantities ...
Vassos Soteriou, Noel Eisley, Li-Shiuan Peh