2784 search results - page 7 / 557 » Instruction Level Parallelism |
CGO
2005
IEEE
14 years 3 months ago
2005
IEEE
In this paper, we describe how to extend the concept of superword-level parallelization (SLP), used for multimedia extension architectures, so that it can be applied in the presen...
HPCA
2007
IEEE
14 years 10 months ago
2007
IEEE
A thread executing on a simultaneous multithreading (SMT) processor that experiences a long-latency load will eventually stall while holding execution resources. Existing long-lat...
ISCA
2002
IEEE
14 years 2 months ago
2002
IEEE
Instruction window size is an important design parameter for many modern processors. Large instruction windows offer the potential advantage of exposing large amounts of instructi...
DSD
2002
IEEE
14 years 2 months ago
2002
IEEE
Modern microprocessors schedule instructions dynamically in order to exploit instruction-level parallelism. It is necessary to increase instruction window size for improving instr...
ICCD
2002
IEEE
14 years 6 months ago
2002
IEEE
Embedded processors are increasingly deployed in applications requiring high performance with good real-time characteristics whilst being low power. Parallelism has to be extracte...