2784 search results - page 99 / 557 » Instruction Level Parallelism |
125
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HPCA
2006
IEEE
16 years 2 months ago
2006
IEEE
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
139
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IEEEPACT
2005
IEEE
15 years 8 months ago
2005
IEEE
VLIW architectures are popular in embedded systems because they offer high-performance processing at low cost and energy. The major problem with traditional VLIW designs is that t...
93
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ARCS
2004
Springer
15 years 8 months ago
2004
Springer
: We investigated different parallel SIMD (single instruction multiple data) architectures based on pure programmable and reconfigurable approaches for their appropriateness for in...
99
Voted
ISPAN
1997
IEEE
15 years 6 months ago
1997
IEEE
Loop unrolling is one of the most promising parallelization techniques, because the nature of programs causes most of the processing time to be spent in their loops. Unrolling not...
128
Voted
CGO
2006
IEEE
15 years 8 months ago
2006
IEEE
As the amount of available silicon resources on one chip increases, we have seen the advent of ever increasing parallel resources integrated on-chip. Many architectures use these ...