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» Instruction Precomputation for Fault Detection
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ISCA
2003
IEEE
136views Hardware» more  ISCA 2003»
14 years 22 days ago
Transient-Fault Recovery for Chip Multiprocessors
To address the increasing susceptibility of commodity chip multiprocessors (CMPs) to transient faults, we propose Chiplevel Redundantly Threaded multiprocessor with Recovery (CRTR...
Mohamed A. Gomaa, Chad Scarbrough, Irith Pomeranz,...
DSD
2010
IEEE
149views Hardware» more  DSD 2010»
13 years 5 months ago
Low Latency Recovery from Transient Faults for Pipelined Processor Architectures
Abstract--Recent technology trends have made radiationinduced soft errors a growing threat to the reliability of microprocessors, a problem previously only known to the aerospace i...
Marcus Jeitler, Jakob Lechner
CASES
2008
ACM
13 years 9 months ago
A light-weight cache-based fault detection and checkpointing scheme for MPSoCs enabling relaxed execution synchronization
While technology advances have made MPSoCs a standard architecture for embedded systems, their applicability is increasingly being challenged by dramatic increases in the amount o...
Chengmo Yang, Alex Orailoglu
DFT
2008
IEEE
151views VLSI» more  DFT 2008»
13 years 9 months ago
Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller
This paper presents a concurrent error detection technique for the control logic of a modern microprocessor. Our method is based on execution time prediction for each instruction ...
Michail Maniatakos, Naghmeh Karimi, Yiorgos Makris...
TVCG
2010
156views more  TVCG 2010»
13 years 5 months ago
Yet Faster Ray-Triangle Intersection (Using SSE4)
—Ray-triangle intersection is an important algorithm, not only in the field of realistic rendering (based on ray tracing), but also in physics simulation, collision detection, m...
Jirí Havel, Adam Herout