113 search results - page 18 / 23 » Instruction Scheduling Based on Subgraph Isomorphism for a H... |
ICCD
2008
IEEE
14 years 4 months ago
2008
IEEE
— Embedded processors are required to achieve high performance while running on batteries. Thus, they must exploit all the possible means available to reduce energy consumption w...
ICPP
2008
IEEE
14 years 1 months ago
2008
IEEE
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
ICPADS
2006
IEEE
14 years 1 months ago
2006
IEEE
One of the major factors that can potentially slow down widespread use of embedded chip multiprocessors is lack of efficient software support. In particular, automated code paral...
HPCA
2000
IEEE
13 years 12 months ago
2000
IEEE
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
IPPS
1998
IEEE
13 years 11 months ago
1998
IEEE
Instruction scheduling methods based on the construction of state diagrams (or automata) have been used for architectures involving deeply pipelined function units. However, the s...