113 search results - page 5 / 23 » Instruction Scheduling Based on Subgraph Isomorphism for a H... |
124
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CF
2004
ACM
15 years 8 months ago
2004
ACM
Current instruction fetch policies in SMT processors are oriented towards optimization of overall throughput and/or fairness. However, they provide no control over how individual ...
131
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IEEEPACT
2002
IEEE
15 years 8 months ago
2002
IEEE
Traditional compilers perform their code generation tasks based on a fixed, pre-determined instruction set. This paper describes the implementation of a compiler that determines ...
151
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CASES
2005
ACM
15 years 5 months ago
2005
ACM
Instruction set customization accelerates the performance of applications by compressing the length of critical dependence paths and reducing the demands on processor resources. W...
146
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HPCC
2009
Springer
15 years 8 months ago
2009
Springer
Usual cache optimisation techniques for high performance computing are difficult to apply in embedded VLIW applications. First, embedded applications are not always well structur...
128
Voted
DAC
1999
ACM
16 years 4 months ago
1999
ACM
This paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using Relative Timing. This method...