113 search results - page 7 / 23 » Instruction Scheduling Based on Subgraph Isomorphism for a H... |
ASAP
2004
IEEE
13 years 11 months ago
2004
IEEE
We describe a general-purpose processor architecture for accelerating public-key computations on server systems that demand high performance and flexibility to accommodate large n...
ICCD
2005
IEEE
14 years 1 months ago
2005
IEEE
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...
SAC
2006
ACM
14 years 1 months ago
2006
ACM
Esterel is a concurrent synchronous language for developing reactive systems. As an alternative to the classical software and hardware synthesis paths, the reactive processing app...
IEEEPACT
2002
IEEE
14 years 12 days ago
2002
IEEE
Many modern embedded processors (esp. DSPs) support partitioned memory banks (also called X-Y memory or dual bank memory) along with parallel load/store instructions to achieve co...
ISCC
2008
IEEE
14 years 1 months ago
2008
IEEE
We propose efficient scheduling algorithms for downlink MIMO-CDMA systems using zero forcing beamforming to achieve high system throughput with low computational complexity. Base...