138 search results - page 15 / 28 » Instruction Scheduling and Executable Editing |
CGO
2003
IEEE
14 years 1 months ago
2003
IEEE
A dynamic binary translation system for a co-designed virtual machine is described and evaluated. The underlying hardware directly executes an accumulator-oriented instruction set...
ISCAS
1999
IEEE
14 years 6 days ago
1999
IEEE
The energy usage of computer systems is becoming important, especially for portablebattery-operated applications and embedded systems. A significant reduction in the energy consum...
IISWC
2008
IEEE
14 years 2 months ago
2008
IEEE
Heterogeneous multi-core processors are attractive for power efficient computing because of their ability to meet varied resource requirements of diverse applications in a workloa...
HPCA
2006
IEEE
14 years 8 months ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
MICRO
1997
IEEE
14 years 4 days ago
1997
IEEE
Predicated execution is a promising architectural feature for exploiting instruction-level parallelism in the presence of control flow. Compiling for predicated execution involve...