369 search results - page 4 / 74 » Instruction set mapping for performance optimization |
ISCA
1998
IEEE
13 years 11 months ago
1998
IEEE
For maximum performance, an out-of-order processor must issue load instructions as early as possible, while avoiding memory-order violations with prior store instructions that wri...
JCP
2008
13 years 7 months ago
2008
A huge application domain, in particular, wireless and handheld devices strongly requires flexible and powerefficient hardware with high performance. This can only be achieved with...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
The H.264/AVC standard defines an in-loop de- instructions, available in current multimedia SIMD instruction blocking filter which is used in both the encoder and decoder. This set...
CASES
2004
ACM
14 years 15 days ago
2004
ACM
ScratchPad Memories (SPMs) are commonly used in embedded systems because they are more energy-efficient than caches and enable tighter application control on the memory hierarchy...
ISCA
2002
IEEE
14 years 2 hour ago
2002
IEEE
The number of pipeline stages separating dynamic instruction scheduling from instruction execution has increased considerably in recent out-of-order microprocessor implementations...