32 search results - page 6 / 7 » Instruction trace compression for rapid instruction cache si... |
JUCS
2000
13 years 6 months ago
2000
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
ARVLSI
1997
IEEE
13 years 11 months ago
1997
IEEE
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...
DATE
2002
IEEE
13 years 12 months ago
2002
IEEE
This paper describes the AccuPower toolset -- a set of simulation tools accurately estimating the power dissipation within a superscalar microprocessor. AccuPower uses a true hard...
CCGRID
2010
IEEE
13 years 6 months ago
2010
IEEE
—While computing speed continues increasing rapidly, data-access technology is lagging behind. Data-access delay, not the processor speed, becomes the leading performance bottlen...
HPCA
2003
IEEE
14 years 7 months ago
2003
IEEE
Java-based middleware, and application servers in particular, are rapidly gaining importance as a new class of workload for commercial multiprocessor servers. SPEC has recognized ...