29 search results - page 3 / 6 » Integrating BIST Techniques for On-Line SoC Testing |
VTS
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents the design and experimental results of fully integrated CMOS power sensors for RF built-in self-test (BIST) applications. Using a standard 0.18- m CMOS process...
ET
2002
13 years 7 months ago
2002
LVDS is the acronym for Low-Voltage-DifferentialSignaling and is described in both the ANSI/TIA/EIA644 and IEEE 1596.3 standards. High performance yet Low Power and EMI have made ...
VTS
2002
IEEE
14 years 10 days ago
2002
IEEE
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
VLSID
2004
IEEE
14 years 7 months ago
2004
IEEE
Recent research for testable designs has focussed on inserting test structures by re-arranging an Register-TransferLevel (RTL) data path generated from a behavioural description t...
CSREAESA
2009
13 years 8 months ago
2009
Two embedded processor based fault injection case studies are presented which are applicable to Field Programmable Gate Arrays (FPGAs) and FPGA cores in configurable System-on-Chip...