71 search results - page 8 / 15 » Integrating Path and Timing Analysis Using Instruction-Level... |
FPGA
2007
ACM
14 years 1 months ago
2007
ACM
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
— Accurate analysis of VLSI interconnects is essential to the performance-driven synthesis and layout of integrated circuits. Existing techniques are based on either simulation, ...
VISUALIZATION
2003
IEEE
14 years 23 days ago
2003
IEEE
This paper describes the work of a team of researchers in computer graphics, geometric computing, and civil engineering to produce a visualization of the September 2001 attack on ...
TCAD
2008
13 years 7 months ago
2008
Three-dimensional integration has the potential to improve the communication latency and integration density of chip-level multiprocessors (CMPs). However, the stacked highpower de...
CORR
2007
Springer
13 years 7 months ago
2007
Springer
— In order to optimize the costs and time of design of the new products while improving their quality, concurrent engineering is based on the digital model of these products, the...