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DATE
2000
IEEE
88views Hardware» more  DATE 2000»
14 years 2 days ago
Techniques for Reducing Read Latency of Core Bus Wrappers
Today’s system-on-a-chip designs consist of many cores. To enable cores to be easily integrated into different systems, many propose creating cores with their internal logic sep...
Roman L. Lysecky, Frank Vahid, Tony Givargis
EH
2000
IEEE
183views Hardware» more  EH 2000»
14 years 2 days ago
A Reconfigurable Platform for the Automatic Synthesis of Analog Circuits
Reconfigurable chips are integrated circuits whose internal connections can be programmed by the user to attend a specific application. Field Programmable Gate Arrays (FPGAs) and ...
Ricardo Salem Zebulum, Cristina Costa Santini, Hel...
DOLAP
2000
ACM
14 years 1 days ago
Automatically Generating OLAP Schemata from Conceptual Graphical Models
Generating tool specific schemata and configuration information for OLAP database tools from conceptual graphical models is an important prerequisite for a comprehensive tool supp...
Karl Hahn, Carsten Sapia, Markus Blaschka
CBMS
1999
IEEE
13 years 12 months ago
Decision Support System for Multiuser Remote Microscopy in Telepathology
Recent advances in networking, robotics, and computer technology allow today realtime diagnosis, consultation, and education by using images obtained through remote microscopy. Th...
Dorin Comaniciu, Bogdan Georgescu, Peter Meer, Wen...
ICCD
1999
IEEE
136views Hardware» more  ICCD 1999»
13 years 12 months ago
ActiveOS: Virtualizing Intelligent Memory
Current trends in DRAM memory chip fabrication have led many researchers to propose \intelligent memory" architectures that integrate microprocessors or logic with memory. Su...
Mark Oskin, Frederic T. Chong, Timothy Sherwood