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» Integrating an Agile Process in a Model Driven Architecture
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DAC
2002
ACM
14 years 8 months ago
DRG-cache: a data retention gated-ground cache for low power
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
Amit Agarwal, Hai Li, Kaushik Roy
IFM
2004
Springer
125views Formal Methods» more  IFM 2004»
14 years 26 days ago
Formally Justifying User-Centred Design Rules: A Case Study on Post-completion Errors
Abstract. Interactive systems combine a human operator with a computer. Either may be a source of error. The veri cation processes used must ensure both the correctness of the comp...
Paul Curzon, Ann Blandford
EMSOFT
2003
Springer
14 years 21 days ago
Event Correlation: Language and Semantics
Abstract. Event correlation is a service provided by middleware platforms that allows components in a publish/subscribe architecture to subscribe to patterns of events rather than ...
César Sánchez, Sriram Sankaranarayan...
ICRA
1995
IEEE
188views Robotics» more  ICRA 1995»
13 years 11 months ago
Fast Approximation of Range Images by Triangular Meshes Generated through Adaptive Randomized Sampling
This paper describes and evaluates an efficient technique that allows the fast generation of 3D triangular meshes from range images avoiding optimization procedures. Such a tool ...
Miguel Angel García
GLVLSI
2002
IEEE
108views VLSI» more  GLVLSI 2002»
14 years 13 days ago
Protected IP-core test generation
Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte...
Alessandro Fin, Franco Fummi