Sciweavers

159 search results - page 16 / 32
» Integrating optimization and simulation: research and practi...
Sort
View
DAC
2003
ACM
14 years 8 months ago
Multilevel global placement with retiming
Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous designs, this requires retiming and pipel...
Jason Cong, Xin Yuan
ICCAD
1997
IEEE
137views Hardware» more  ICCAD 1997»
13 years 11 months ago
Optimization techniques for high-performance digital circuits
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
Chandramouli Visweswariah
SECON
2008
IEEE
14 years 1 months ago
Optimal Buffer Management Policies for Delay Tolerant Networks
—Delay Tolerant Networks are wireless networks where disconnections may occur frequently due to propagation phenomena, node mobility, and power outages. Propagation delays may al...
Amir Krifa, Chadi Barakat, Thrasyvoulos Spyropoulo...
IWCMC
2010
ACM
13 years 5 months ago
Dynamic load balancing and throughput optimization in 3GPP LTE networks
Load imbalance that deteriorates the system performance is a severe problem existing in 3GPP LTE networks. To deal with this problem, we propose in this paper a load balancing fra...
Hao Wang, Lianghui Ding, Ping Wu, Zhiwen Pan, Nan ...
SP
2008
IEEE
14 years 1 months ago
Preventing Memory Error Exploits with WIT
Attacks often exploit memory errors to gain control over the execution of vulnerable programs. These attacks remain a serious problem despite previous research on techniques to pr...
Periklis Akritidis, Cristian Cadar, Costin Raiciu,...