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FPGA
2003
ACM
123views FPGA» more  FPGA 2003»
14 years 3 months ago
Wire type assignment for FPGA routing
The routing channels of an FPGA consist of wire segments of various types providing the tradeoff between performance and routability. In the routing architectures of recently dev...
Seokjin Lee, Hua Xiang, D. F. Wong, Richard Y. Sun
ICCAD
1997
IEEE
90views Hardware» more  ICCAD 1997»
14 years 2 months ago
A hierarchical decomposition methodology for multistage clock circuits
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar
DATE
2009
IEEE
88views Hardware» more  DATE 2009»
14 years 1 months ago
A generic framework for scan capture power reduction in fixed-length symbol-based test compression environment
Growing test data volume and overtesting caused by excessive scan capture power are two of the major concerns for the industry when testing large integrated circuits. Various test...
Xiao Liu, Qiang Xu
APWEB
2006
Springer
14 years 1 months ago
Automatically Constructing Descriptive Site Maps
Rapid increase in the number of pages on web sites, and widespread use of search engine optimization techniques, lead to web sites becoming difficult to navigate. Traditional site ...
Pavel Dmitriev, Carl Lagoze
ATAL
2006
Springer
14 years 1 months ago
ANEMONE: an effective minimal ontology negotiation environment
Communication in open heterogeneous multi agent systems is hampered by lack of shared ontologies. To overcome these problems, we propose a layered communication protocol which inc...
Jurriaan van Diggelen, Robbert-Jan Beun, Frank Dig...