1928 search results - page 287 / 386 » Integrity Constraints in OWL |
ISPD
2009
ACM
14 years 4 months ago
2009
ACM
Gate sizing and threshold voltage (Vt) assignment are popular techniques for circuit timing and power optimization. Existing methods, by and large, are either sensitivity-driven h...
EDBT
2009
ACM
14 years 4 months ago
2009
ACM
We consider the following scenario for a mapping system: given a source schema, a target schema, and a set of value correspondences between these two schemas, generate an executab...
DATE
2009
IEEE
14 years 4 months ago
2009
IEEE
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
ICC
2009
IEEE
14 years 4 months ago
2009
IEEE
—At present there is a strong worldwide push toward bringing fiber closer to individual homes and businesses. Another evolutionary step is the cost-effective all-optical integra...
RECONFIG
2009
IEEE
14 years 4 months ago
2009
IEEE
Abstract—Integrated circuits for very high-speed telecommunication protocols often use ASICs, due to their strict timing constraints. This scenario is changing, since modern FPGA...