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DAC
2002
ACM
14 years 8 months ago
IP delivery for FPGAs using Applets and JHDL
This paper introduces an FPGA IP evaluation and delivery system that operates within Java applets. The use of such applets allows designers to create, evaluate, test, and obtain F...
Michael J. Wirthlin, Brian McMurtrey
WWW
2004
ACM
14 years 8 months ago
OREL: an ontology-based rights expression language
This paper proposes an Ontology-based Rights Expression Language, called OREL. Based on OWL Web Ontology Language, OREL allows not only users but also machines to handle digital r...
Yuzhong Qu, Xiang Zhang, Huiying Li
VLSID
2005
IEEE
158views VLSI» more  VLSID 2005»
14 years 8 months ago
Algorithmic Implementation of Low-Power High Performance FIR Filtering IP Cores
This paper presents two schemes for the implementation of high performance and low power FIR filtering Intellectual Property (IP) cores. Low power is achieved through the utilizat...
C. H. Wang, Ahmet T. Erdogan, Tughrul Arslan
VLSID
2004
IEEE
119views VLSI» more  VLSID 2004»
14 years 8 months ago
Bridge Over Troubled Wrappers: Automated Interface Synthesis
System-on-Chip (SoC) design methodologies rely heavily on reuse of intellectual property (IP) blocks. IP reuse is a labour intensive and time consuming process as IP blocks often ...
Vijay D'Silva, S. Ramesh, Arcot Sowmya
ICCD
2005
IEEE
128views Hardware» more  ICCD 2005»
14 years 4 months ago
Automatic Synthesis of Composable Sequential Quantum Boolean Circuits
This paper presents a methodology to transfer self-timed circuit specifications into sequential quantum Boolean circuits (SQBCs) and composable SQBCs (CQBCs). State graphs (SGs) a...
Li-Kai Chang, Fu-Chiung Cheng