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ICCAD
2001
IEEE
100views Hardware» more  ICCAD 2001»
14 years 7 months ago
Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets
In deep submicron VLSI circuits, interconnect reliability due to electromigration and thermal effects is fast becoming a serious design issue particularly for long signal lines. T...
Kaustav Banerjee, Amit Mehrotra
PDP
2010
IEEE
14 years 5 months ago
Impact of Parallel Workloads on NoC Architecture Design
— Due to the multi-core processors, the importance of parallel workloads has increased considerably. However, manycore chips demand new interconnection strategies, since traditio...
Henrique Cota de Freitas, Lucas Mello Schnorr, Mar...
ICMCS
2005
IEEE
133views Multimedia» more  ICMCS 2005»
14 years 4 months ago
Architecture for area-efficient 2-D transform in H.264/AVC
As the VLSI technology advances continuously, ASIC can easily achieve the required performance and most of them are actually over-designed. Thus, architecture shrinking is inevita...
Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei ...
FCCM
2003
IEEE
92views VLSI» more  FCCM 2003»
14 years 3 months ago
Perturbation Analysis for Word-length Optimization
This paper introduces a design tool and its associated procedures for determining the sensitivity of outputs in a digital signal processing design to small errors introduced by ro...
George A. Constantinides
ISPD
2005
ACM
205views Hardware» more  ISPD 2005»
14 years 4 months ago
Coupling aware timing optimization and antenna avoidance in layer assignment
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
Di Wu, Jiang Hu, Rabi N. Mahapatra