154 search results - page 4 / 31 » Interconnect Optimization Strategies for High-Performance VL... |
125
Voted
DAC
2005
ACM
16 years 4 months ago
2005
ACM
Device and interconnect fabrics at the nanoscale will have a density of defects and susceptibility to transient faults far exceeding those of current silicon technologies. In this...
123
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GLVLSI
2009
IEEE
15 years 10 months ago
2009
IEEE
Resource based optimization for high performance integrated circuits is presented. The methodology is applied to simultaneous shield and repeater insertion, resulting in minimum c...
119
Voted
CLUSTER
2006
IEEE
15 years 9 months ago
2006
IEEE
As new processor and memory architectures advance, clusters start to be built from larger SMP systems, which makes MPI intra-node communication a critical issue in high performanc...
127
Voted
ICCD
2008
IEEE
16 years 14 days ago
2008
IEEE
— To address the performance limitation brought by the scaling issues of on-chip global wires, a new configuration for global wiring using on-chip lossy transmission lines(T-lin...
125
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ASPDAC
2009
ACM
15 years 10 months ago
2009
ACM
— To address the performance limitation brought by the scaling issues of on-chip global wires, a new configuration for global wiring using on-chip lossy transmission lines is pr...