44 search results - page 8 / 9 » Interconnect design considerations for large NUCA caches |
SIGMOD
2006
ACM
14 years 10 months ago
2006
ACM
For Web applications in which the database component is the bottleneck, scalability can be provided by a third-party Database Scalability Service Provider (DSSP) that caches appli...
ICPP
2006
IEEE
14 years 3 months ago
2006
IEEE
— This paper focuses on the transfer of large data in SMP systems. Achieving good performance for intranode communication is critical for developing an efficient communication s...
MICRO
2002
IEEE
13 years 9 months ago
2002
IEEE
Power consumption and power density for the Translation Lookaside Buffer (TLB) are important considerations not only in its design, but can have a consequence on cache design as w...
MICRO
2006
IEEE
14 years 3 months ago
2006
IEEE
3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die ...
DAC
2006
ACM
14 years 10 months ago
2006
ACM
Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several othe...