54 search results - page 6 / 11 » Interconnect design for deep submicron ICs |
ICCAD
2000
IEEE
13 years 11 months ago
2000
IEEE
Coupling effects between on-chip interconnects must be addressed in ultra deep submicron VLSI and system-on-a-chip (SoC) designs. A new low-power bus encoding scheme is proposed t...
IOLTS
2003
IEEE
13 years 12 months ago
2003
IEEE
On-chip global interconnections in very deep submicron technology (VDSM) ICs are becoming more sensitive and prone to errors caused by power supply noise, crosstalk noise, delay v...
DAC
1999
ACM
13 years 11 months ago
1999
ACM
In deep submicron technology, IR-drop and clock skew issues become more crucial to the functionality of chip. This paper presents a oorplan-based power and clock distribution meth...
TC
2008
13 years 6 months ago
2008
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
SLIP
2003
ACM
13 years 12 months ago
2003
ACM
The problem of interconnect architecture arises when an array of processors needs to be integrated on one chip. With the deep sub-micron technology, devices become cheap while wir...