816 search results - page 124 / 164 » Interconnect design methods for memory design |
RTAS
2006
IEEE
2006
IEEE
METERG: Measurement-Based End-to-End Performance Estimation Technique in QoS-Capable Multiprocessors
14 years 1 months ago
Multiprocessor systems present serious challenges in the design of real-time systems due to the wider variation of execution time of an instruction sequence compared to a uniproce...
ICCAD
2008
IEEE
14 years 4 months ago
2008
IEEE
—The microprocessor verification challenge becomes higher in the on-chip bus (OCB) than in the unit-level. Especially for the external interrupts, since they interface with othe...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—Flash-based FPGAs are increasingly demanded in safety critical fields, in particular space and avionic ones, due to their non-volatile configuration memory. Although they are al...
ISLPED
2006
ACM
14 years 1 months ago
2006
ACM
Buffering more in-flight instructions in an out-of-order microprocessor is a straightforward and effective method to help tolerate the long latencies generally associated with ...
FSE
1993
Springer
13 years 11 months ago
1993
Springer
Parallel FFT-Hashing was designed by C. P. Schnorr and S. Vaudenay in 1993. The function is a simple and light weight hash algorithm with 128-bit digest. Its basic component is a m...