816 search results - page 129 / 164 » Interconnect design methods for memory design |
ISLPED
2003
ACM
14 years 26 days ago
2003
ACM
High-performance processors use a large set–associative L1 data cache with multiple ports. As clock speeds and size increase such a cache consumes a significant percentage of t...
ISORC
2002
IEEE
14 years 16 days ago
2002
IEEE
Preemption threshold scheduling (PTS) provides prominent benefits for fixed priority scheduling such as increased schedulability, reduced context switches, and decreased memory re...
MMMACNS
2001
Springer
14 years 1 days ago
2001
Springer
Abstract. Many design flaws and incorrect analyses of cryptographic protoAppeared in the Proceedings of the First International Workshop on Mathematical Methods, Models and Archit...
IPPS
1999
IEEE
13 years 12 months ago
1999
IEEE
An e cient implementations of the main building block in the RSA cryptographic scheme is achieved by mapping a bit-level systolic array for modular exponentiation onto Xilinx FPGAs...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...