816 search results - page 4 / 164 » Interconnect design methods for memory design |
VLSISP
2008
13 years 7 months ago
2008
Each new semiconductor technology node brings smaller, faster transistors and smaller, slower wires. In particular, long interconnect wires in modern FPGAs now require rebuffering ...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
— New back-end design for manufacturability rules have brought guarantee rules for interconnect matching. These rules indicate a certain capacitance matching guarantee given spac...
DAC
2000
ACM
14 years 8 months ago
2000
ACM
Due to the large die sizes and tight relative clock skew margins, the impact of interconnect manufacturing variations on the clock skew in today's gigahertz microprocessors c...
WMPI
2004
ACM
14 years 27 days ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
— In this paper, we present a high-level power model to estimate the power consumption in semi-global and global interconnects. Such interconnects are used for communications bet...