816 search results - page 59 / 164 » Interconnect design methods for memory design |
ICMCS
2005
IEEE
14 years 2 months ago
2005
IEEE
The paper presents a high-performance architecture of the bit-plane coder for the embedded block coding algorithm in JPEG 2000. The architecture adopts a pipeline structure and is...
PUC
2008
13 years 8 months ago
2008
Although many recent systems have been built to support Information Capture and Retrieval (ICR), these have not generally been successful. This paper presents studies that evaluate...
VTS
2007
IEEE
14 years 3 months ago
2007
IEEE
: Soft faults in DRAMs are faults that do not get sensitized directly after an operation is performed, but require a time to pass before the fault can be detected. Tests developed ...
WWW
2006
ACM
14 years 9 months ago
2006
ACM
We present a novel model for validating and improving the content and structure organization of a website. This model studies the website as a graph and evaluates its interconnect...
DATE
2010
IEEE
14 years 2 months ago
2010
IEEE
—Multi-Processor System-on-Chips (MPSoCs) exploit task-level parallelism to achieve high computation throughput, but concurrent memory accesses from multiple PEs may cause memory...