Sciweavers

816 search results - page 83 / 164
» Interconnect design methods for memory design
Sort
View
PVLDB
2011
12 years 11 months ago
Merging What's Cracked, Cracking What's Merged: Adaptive Indexing in Main-Memory Column-Stores
Adaptive indexing is characterized by the partial creation and refinement of the index as side effects of query execution. Dynamic or shifting workloads may benefit from prelimi...
Stratos Idreos, Stefan Manegold, Harumi A. Kuno, G...
CHI
1998
ACM
14 years 1 months ago
Insight Lab: An Immersive Team Environment Linking Paper, Displays, and Data
The Insight Lab is an immersive environment designed to support teams who create design requirements documents. Requirements emerge from a deep understanding of a problem domain, ...
Beth M. Lange, Mark A. Jones, James L. Meyers
ASPDAC
2004
ACM
85views Hardware» more  ASPDAC 2004»
14 years 2 months ago
Integrating buffer planning with floorplanning for simultaneous multi-objective optimization
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance and signal integrity. Buffer insertion is one...
Yi-Hui Cheng, Yao-Wen Chang
CODES
2008
IEEE
14 years 3 months ago
Distributed flit-buffer flow control for networks-on-chip
The combination of flit-buffer flow control methods and latency-insensitive protocols is an effective solution for networks-on-chip (NoC). Since they both rely on backpressure...
Nicola Concer, Michele Petracca, Luca P. Carloni
CIKM
2008
Springer
13 years 11 months ago
Classifying networked entities with modularity kernels
Statistical machine learning techniques for data classification usually assume that all entities are i.i.d. (independent and identically distributed). However, real-world entities...
Dell Zhang, Robert Mao