816 search results - page 84 / 164 » Interconnect design methods for memory design |
SC
2009
ACM
14 years 3 months ago
2009
ACM
We present ECC FIFO, a mechanism enabling two-tiered last-level cache error protection using an arbitrarily strong tier-2 code without increasing on-chip storage. Instead of addin...
DAC
2010
ACM
14 years 27 days ago
2010
ACM
State-of-the-art automatic reliability analyses as used in system-level design approaches mainly rely on Binary Decision Diagrams (BDDs) and, thus, face two serious problems: (1) ...
ISMVL
2010
IEEE
14 years 1 months ago
2010
IEEE
This paper proposes a new architecture for memorybased floating-point numeric function generators (NFGs). The design method uses piecewise-split edge-valued multivalued decision ...
PLDI
2009
ACM
14 years 3 months ago
2009
ACM
The client computing platform is moving towards a heterogeneous architecture consisting of a combination of cores focused on scalar performance, and a set of throughput-oriented c...
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
Abstract—To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between...