816 search results - page 97 / 164 » Interconnect design methods for memory design |
IPPS
2002
IEEE
14 years 19 days ago
2002
IEEE
Accurate estimation of signal delay is critical to the design and verification of VLSI circuits. At very high frequencies, signal delay in circuits with small feature sizes is do...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
Current technology trends have led to the growing impact of both inter-die and intra-die process variations on circuit performance. While it is imperative to model parameter varia...
SLIP
2009
ACM
14 years 2 months ago
2009
ACM
As technology advances, 3D ICs are introduced for alleviating the interconnect problem coming with shrinking feature size and increasing integration density. In 3D ICs, one of the...
DDECS
2007
IEEE
14 years 2 months ago
2007
IEEE
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
ICRA
2005
IEEE
14 years 1 months ago
2005
IEEE
- We are developing a process to quickly prototype millirobotic systems in which the approach is to identify and develop a construction kit for fabricating almost any design, simil...