816 search results - page 9 / 164 » Interconnect design methods for memory design |
SCS
2004
13 years 9 months ago
2004
Limitations in scope but also difficulties with the efficiency and scalability of present algorithms seem to have so far limited the industrial uptake of existing automated FMEA t...
VLSID
2000
IEEE
13 years 12 months ago
2000
IEEE
The test signal method can be used to measure and model inductance parameters (self and mutual) of a very small interconnect especially in highdensity IC’s by using a test signa...
ISCA
2010
IEEE
14 years 18 days ago
2010
IEEE
The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of el...
3DIC
2009
IEEE
14 years 2 months ago
2009
IEEE
- This paper describes a new architectural paradigm for fully connected, single-hop system level interconnection networks. The architecture is scalable enough to meet the needs of ...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
- With the increasing demand for SoCs to include rich functionality, SoCs are being designed with hundreds of small memories with different sizes and frequencies. If memory BIST lo...