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GECCO
2007
Springer
188views Optimization» more  GECCO 2007»
14 years 1 months ago
Using genetic algorithms for naval subsystem damage assessment and design improvements
Some auxiliary systems of next generation naval ships will utilize distributed automatic control. Such distributed control systems will use interconnected sensors, actuators, cont...
Christopher McCubbin, David Scheidt, Oliver Bandte...
VLSID
2002
IEEE
116views VLSI» more  VLSID 2002»
14 years 8 months ago
Efficient Macromodeling for On-Chip Interconnects
The improved T and improved n models are proposed for onchip interconnect macromodeling. Using global approximations, simple approximation frames are derived and applied to modeli...
Qinwei Xu, Pinaki Mazumder
SLIP
2009
ACM
14 years 2 months ago
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs
Individual dies in 3D integrated circuits are connected using throughsilicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power ...
Dae Hyun Kim, Saibal Mukhopadhyay, Sung Kyu Lim
ISVLSI
2005
IEEE
80views VLSI» more  ISVLSI 2005»
14 years 1 months ago
Sensitivity Analysis of a Cluster-Based Interconnect Model for FPGAs
Mesh interconnect can be efficiently utilized while tree networks encourage the short routing distances. In this paper, we present the property analysis of a cluster-based interc...
Renqiu Huang, Ranga Vemuri
MICRO
2007
IEEE
115views Hardware» more  MICRO 2007»
14 years 1 months ago
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...
Naveen Muralimanohar, Rajeev Balasubramonian, Norm...