731 search results - page 22 / 147 » Interconnect modeling for improved system-level design optim... |
ICCD
1994
IEEE
13 years 11 months ago
1994
IEEE
This paper presents a simple and robust method of designing the lossy-transmission-line interconnects in a network for multichip modules. This method uses wire-sizing entirely to ...
SLIP
2003
ACM
14 years 24 days ago
2003
ACM
Aggressive process scaling and increasing clock rates have made crosstalk noise an important issue in VLSI design. Switching on adjacent wires on long bus lines can increase delay...
WWW
2006
ACM
14 years 8 months ago
2006
ACM
We present a novel model for validating and improving the content and structure organization of a website. This model studies the website as a graph and evaluates its interconnect...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
In recent years, increasing manufacturing density has allowed the development of Multi-Processor Systems-on-Chip (MPSoCs). Application-Specific Instruction Set Processors (ASIPs)...
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
In this paper we propose a novel analog design optimization methodology to address two key aspects of top-down system-level design: (1) how to optimally compare and select analog ...