731 search results - page 59 / 147 » Interconnect modeling for improved system-level design optim... |
BROADNETS
2006
IEEE
14 years 1 months ago
2006
IEEE
— This paper presents the design and dimensioning optimization of a novel optical network structure, called the Petaweb, having a total capacity of several Pb/s (1015 bit/s). Its...
EUC
2006
Springer
13 years 11 months ago
2006
Springer
Abstract. As process technology scales down, power wall starts to hinder improvements in processor performance. Performance optimization has to proceed under a power constraint. Th...
CODES
2002
IEEE
14 years 20 days ago
2002
IEEE
High-speed serial network interfaces are gaining wide use in connecting multiple processors and peripherals in modern embedded systems, thanks to their size advantage and power ef...
CPAIOR
2004
Springer
14 years 1 months ago
2004
Springer
We discuss a di cult optimization problem on a chess-board, requiring equal numbers of black and white queens to be placed on the board so that the white queens cannot attack the b...
ISPD
2009
ACM
14 years 2 months ago
2009
ACM
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...