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    DATE
    2005
    IEEE
    176views Hardware» more  DATE 2005»
    Effective Lower Bounding Techniques for Pseudo-Boolean Optimization
    14 years 1 months ago
    Effective Lower Bounding Techniques for Pseudo-Boolean Optimization
    Download  sat.inesc.pt
    Linear Pseudo-Boolean Optimization (PBO) is a widely used modeling framework in Electronic Design Automation (EDA). Due to significant advances in Boolean Satisfiability (SAT), ...
    Vasco M. Manquinho, João P. Marques Silva
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    DEXA
    2005
    Springer
    77views Database» more  DEXA 2005»
    An Optimal Skew-insensitive Join and Multi-join Algorithm for Distributed Architectures
    14 years 1 months ago
    An Optimal Skew-insensitive Join and Multi-join Algorithm for Distributed Architectures
    Download  www.univ-orleans.fr
    Abstract. The development of scalable parallel database systems requires the design of efficient algorithms for the join operation which is the most frequent and expensive operatio...
    Mostafa Bamha
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    ICASSP
    2010
    IEEE
    150views Signal Processing» more  ICASSP 2010»
    Optimizing spectral subtraction and wiener filtering for robust speech recognition in reverberant and noisy conditions
    13 years 8 months ago
    Optimizing spectral subtraction and wiener filtering for robust speech recognition in reverberant and noisy conditions
    Download  www.ar.media.kyoto-u.ac.jp
    Speech enhancement is a common approach to address the effects of degradation due to noise and channel contamination. This approach is intended to suppress unwanted signal and rec...
    Randy Gomez, Tatsuya Kawahara
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    WMPI
    2004
    ACM
    220views Computer Architecture» more  WMPI 2004»
    A compressed memory hierarchy using an indirect index cache
    14 years 1 months ago
    A compressed memory hierarchy using an indirect index cache
    Download  www.eecs.umich.edu
    Abstract. The large and growing impact of memory hierarchies on overall system performance compels designers to investigate innovative techniques to improve memory-system efficienc...
    Erik G. Hallnor, Steven K. Reinhardt
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    TVLSI
    2002
    121views more  TVLSI 2002»
    On-chip decoupling capacitor optimization using architectural level prediction
    13 years 7 months ago
    On-chip decoupling capacitor optimization using architectural level prediction
    Download  users.ece.gatech.edu
    Switching activity-generated power-supply grid-noise presents a major obstacle to the reduction of supply voltage in future generation semiconductor technologies. A popular techniq...
    Mondira Deb Pant, Pankaj Pant, D. Scott Wills
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