60 search results - page 3 / 12 » Interface Design for Rationally Clocked GALS Systems |
ICCD
2007
IEEE
14 years 6 months ago
2007
IEEE
Building fully synchronous VLSI circuits is becoming less viable as circuit geometries evolve. However, before the adoption of purely asynchronous strategies in VLSI design, globa...
ISCA
2002
IEEE
14 years 2 months ago
2002
IEEE
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
DT
2007
13 years 9 months ago
2007
- This paper presents a new low latency Crossbar design that can be used to interface systems working at different frequencies. For case of multiple input ports contending for same...
ISVLSI
2008
IEEE
14 years 4 months ago
2008
IEEE
The evolution of deep submicron technologies allows the development of increasingly complex Systems on a Chip (SoC). However, this evolution is rendering less viable some well-est...
IPPS
1998
IEEE
14 years 2 months ago
1998
IEEE
This paper? provides a description of our Network Time Interface M-Module NTI supporting high-accuracy external clock synchronization by hardware. The NTI is built around our custo...