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SIGGRAPH
1994
ACM
15 years 8 months ago
FBRAM: a new form of memory optimized for 3D graphics
FBRAM, a new form of dynamic random access memory that greatly accelerates the rendering of Z-buffered primitives, is presented. Two key concepts make this acceleration possible. ...
Michael F. Deering, Stephen A. Schlapp, Michael G....
VLSID
2010
IEEE
173views VLSI» more  VLSID 2010»
15 years 8 months ago
Voltage-Frequency Planning for Thermal-Aware, Low-Power Design of Regular 3-D NoCs
Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. ...
Mohammad Arjomand, Hamid Sarbazi-Azad
WSCG
2004
154views more  WSCG 2004»
15 years 5 months ago
Emulating an Offline Renderer by 3D Graphics Hardware
3D design software has since long employed graphics chips for low-quality real-time previewing. But their dramatically increased computing power now paves the way to accelerate th...
Jörn Loviscach
MJ
2011
288views Multimedia» more  MJ 2011»
14 years 11 months ago
Emulation-based transient thermal modeling of 2D/3D systems-on-chip with active cooling
New tendencies envisage 2D/3D Multi-Processor System-On-Chip (MPSoC) as a promising solution for the consumer electronics market. MPSoCs are complex to design, as they must execute...
Pablo Garcia Del Valle, David Atienza
HPCA
2009
IEEE
16 years 4 months ago
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
Niti Madan, Li Zhao, Naveen Muralimanohar, Anirudd...