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INTEGRATION
2010
70views more  INTEGRATION 2010»
13 years 6 months ago
Thermal modeling and analysis of 3D multi-processor chips
José L. Ayala, Arvind Sridhar, David Cuesta
ASPDAC
2010
ACM
142views Hardware» more  ASPDAC 2010»
13 years 5 months ago
Application-specific 3D Network-on-Chip design using simulated allocation
Pingqiang Zhou, Ping-Hung Yuh, Sachin S. Sapatneka...
TPDS
2010
109views more  TPDS 2010»
13 years 6 months ago
Thermal-Aware Task Scheduling for 3D Multicore Processors
Abstract—A rising horizon in chip fabrication is the 3D integration technology. It stacks two or more dies vertically with a dense, highspeed interface to increase the device den...
Xiuyi Zhou, Jun Yang 0002, Yi Xu, Youtao Zhang, Ji...
DATE
2007
IEEE
86views Hardware» more  DATE 2007»
14 years 1 months ago
Thermally robust clocking schemes for 3D integrated circuits
3D integration of multiple active layers into a single chip is a viable technique that greatly reduces the length of global wires by providing vertical connections between layers....
Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Ta...
3DIC
2009
IEEE
142views Hardware» more  3DIC 2009»
14 years 20 days ago
Electrical-thermal co-analysis for power delivery networks in 3D system integration
- In this paper, an electrical-thermal co-analysis method for power delivery networks in 3D system integration is proposed. For electrical analysis, temperature-dependent electrica...
Jianyong Xie, Daehyun Chung, Madhavan Swaminathan,...