108 search results - page 5 / 22 » Introspective 3D chips |
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
— Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlike transistors, have not followed the same trend. Designing 3D stack architec...
NOCS
2009
IEEE
14 years 2 months ago
2009
IEEE
Design Constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3-D chip stacks an enticing technology solution for m...
DATE
1997
IEEE
13 years 11 months ago
1997
IEEE
An efficient method for the analysis of real 3D conjugate heat transfer for electronic devices is presented. This methodology is based on the coupling of two software : a conducti...
ICPP
2007
IEEE
14 years 1 months ago
2007
IEEE
Three-dimensional Network-on-Chip (3-D NoC) is an emerging research topic exploring the network architecture of 3-D ICs that stack several smaller wafers for reducing wire length ...
DAC
2010
ACM
13 years 11 months ago
2010
ACM
The ever increasing die area of Chip Multiprocessors (CMPs) affects manufacturing yield, resulting in higher manufacture cost. Meanwhile, network-on-chip (NoC) has emerged as a p...