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LCTRTS
2010
Springer
13 years 7 months ago
RNFTL: a reuse-aware NAND flash translation layer for flash memory
In this paper, we propose a hybrid-level flash translation layer (FTL) called RNFTL (Reuse-Aware NFTL) to improve the endurance and space utilization of NAND flash memory. Our bas...
Yi Wang, Duo Liu, Meng Wang, Zhiwei Qin, Zili Shao...
IESS
2007
Springer
165views Hardware» more  IESS 2007»
14 years 4 months ago
Data Reuse Driven Memory and Network-On-Chip Co-Synthesis
NoCs present a possible communication infrastructure solution to deal with increased design complexity and shrinking time-to-market. The communication infrastructure is a signific...
Ilya Issenin, Nikil Dutt
KDD
2012
ACM
190views Data Mining» more  KDD 2012»
12 years 12 days ago
Multi-label hypothesis reuse
Multi-label learning arises in many real-world tasks where an object is naturally associated with multiple concepts. It is well-accepted that, in order to achieve a good performan...
Sheng-Jun Huang, Yang Yu, Zhi-Hua Zhou
CODES
2006
IEEE
14 years 4 months ago
Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
Ilya Issenin, Nikil Dutt
ISPASS
2003
IEEE
14 years 3 months ago
Memory reference reuse latency: Accelerated warmup for sampled microarchitecture simulation
Abstract— This paper proposes to speedup sampled microprocessor simulations by reducing warmup times without sacrificing simulation accuracy. It exploiting the observation that ...
John W. Haskins Jr., Kevin Skadron