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ISCAS
2007
IEEE
104views Hardware» more  ISCAS 2007»
14 years 2 months ago
Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors
Process variation in future technologies can cause severe performance degradation since different parts of the shared Register File (RF) in VLIW processors may operate at various ...
Praveen Raghavan, José L. Ayala, David Atie...
PADS
1996
ACM
14 years 3 hour ago
Time Management in the DoD High Level Architecture
Recently, a considerable amount of effort in the U.S. Department of Defense has been devoted to defining the High Level Architecture (HLA) for distributed simulations. This paper ...
Richard Fujimoto, Richard M. Weatherly
DELOS
2004
13 years 9 months ago
Supporting Information Access in Next Generation Digital Library Architectures
Current developments on Service-oriented Architectures, Peer-to-Peer and Grid computing promise more open and flexible architectures for digital libraries. They will open DL techno...
Ingo Frommholz, Predrag Knezevic, Bhaskar Mehta, C...
ASPLOS
2009
ACM
14 years 8 months ago
Architectural support for SWAR text processing with parallel bit streams: the inductive doubling principle
Parallel bit stream algorithms exploit the SWAR (SIMD within a register) capabilities of commodity processors in high-performance text processing applications such as UTF8 to UTF-...
Robert D. Cameron, Dan Lin
ERSA
2009
146views Hardware» more  ERSA 2009»
13 years 5 months ago
Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor
We present the architecture and programming model for MORA, a coarse-grained reconfigurable processor aimed at multimedia applications. The MORA architecure is a MIMD machine consi...
Wim Vanderbauwhede, Martin Margala, Sai Rahul Chal...