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VMCAI
2005
Springer
14 years 3 months ago
Information Flow Analysis for Java Bytecode
Abstract. We present a context-sensitive compositional analysis of information flow for full (mono-threaded) Java bytecode. Our idea consists in transforming the Java bytecode int...
Samir Genaim, Fausto Spoto
APN
2004
Springer
14 years 3 months ago
Reachability Set Generation for Petri Nets: Can Brute Force Be Smart?
Generating the reachability set is one of the most commonly required step when analyzing the logical or stochastic behavior of a system modeled with Petri nets. Traditional “expl...
Gianfranco Ciardo
DATE
2002
IEEE
94views Hardware» more  DATE 2002»
14 years 2 months ago
Exact Grading of Multiple Path Delay Faults
The problem of fault grading for multiple path delay faults is studied and a method of obtaining the exact coverage is presented. The faults covered are represented and manipulate...
Saravanan Padmanaban, Spyros Tragoudas
EURODAC
1994
IEEE
148views VHDL» more  EURODAC 1994»
14 years 1 months ago
BiTeS: a BDD based test pattern generator for strong robust path delay faults
This paper presents an algorithm for generation of test patterns for strong robust path delay faults, i.e. tests that propagate the fault along a single path and additionally are ...
Rolf Drechsler
ASPDAC
2007
ACM
158views Hardware» more  ASPDAC 2007»
14 years 1 months ago
Symbolic Model Checking of Analog/Mixed-Signal Circuits
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...
David Walter, Scott Little, Nicholas Seegmiller, C...