Sciweavers

601 search results - page 25 / 121
» Lattice-based memory allocation
Sort
View
ISCA
2002
IEEE
159views Hardware» more  ISCA 2002»
14 years 17 days ago
Avoiding Initialization Misses to the Heap
This paper investigates a class of main memory accesses (invalid memory traffic) that can be eliminated altogether. Invalid memory traffic is real data traffic that transfers inva...
Jarrod A. Lewis, Mikko H. Lipasti, Bryan Black
DATE
2010
IEEE
113views Hardware» more  DATE 2010»
14 years 22 days ago
PM-COSYN: PE and memory co-synthesis for MPSoCs
—Multi-Processor System-on-Chips (MPSoCs) exploit task-level parallelism to achieve high computation throughput, but concurrent memory accesses from multiple PEs may cause memory...
Yi-Jung Chen, Chia-Lin Yang, Po-Han Wang
ASPLOS
1998
ACM
13 years 12 months ago
Compiler-Controlled Memory
Optimizations aimed at reducing the impact of memory operations on execution speed have long concentrated on improving cache performance. These efforts achieve a reasonable level...
Keith D. Cooper, Timothy J. Harvey
APLAS
2004
ACM
14 years 1 months ago
Region-Based Memory Management for a Dynamically-Typed Language
Abstract. Region-based memory management scheme has been proposed for the programming language ML. In this scheme, a compiler statically estimates the lifetime of each object by pe...
Akihito Nagata, Naoki Kobayashi, Akinori Yonezawa
ISSS
1996
IEEE
114views Hardware» more  ISSS 1996»
13 years 11 months ago
Flow Graph Balancing for Minimizing the Required Memory Bandwidth
In this paper we present the problem of flow graph balancing for minimizingthe required memory bandwidth. Our goal is to minimize the required memory bandwidth within the given cy...
Sven Wuytack, Francky Catthoor, Gjalt G. de Jong, ...