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ASPDAC
2006
ACM
104views Hardware» more  ASPDAC 2006»
14 years 1 months ago
A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers
—As the VLSI manufacturing technology advances into the deep sub-micron(DSM) era, the mask cost can reach one or two million dollars. Multiple project wafers (MPW) which put diï¬...
Chien-Chang Chen, Wai-Kei Mak
ISPD
2005
ACM
205views Hardware» more  ISPD 2005»
14 years 1 months ago
Coupling aware timing optimization and antenna avoidance in layer assignment
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
Di Wu, Jiang Hu, Rabi N. Mahapatra
MICRO
2008
IEEE
208views Hardware» more  MICRO 2008»
14 years 1 months ago
Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology
— As semiconductor processing techniques continue to scale down, transient faults, also known as soft errors, are increasingly becoming a reliability threat to high-performance m...
Wangyuan Zhang, Tao Li
CAD
1998
Springer
13 years 7 months ago
Tool profile and tool path calculation for free-form thick-layered fabrication
• In several application fields, large sized, free-form objects of various soft materials are widely used. Available layered prototyping technologies cannot be applied for fabri...
Imre Horváth, Joris S. M. Vergeest, Johan J...
IJCM
2002
68views more  IJCM 2002»
13 years 7 months ago
Computing an Optimal Hatching Direction in Layered Manufacturing
In Layered Manufacturing (LM), a prototype of a virtual polyhedral object is built by slicing the object into polygonal layers, and then building the layers one after another. In ...
Jörg Schwerdt, Michiel H. M. Smid, Man Chung ...