1295 search results - page 49 / 259 » Layered manufacturing technologies |
ISPD
1998
ACM
14 years 1 months ago
1998
ACM
In very deep-submicron VLSI, certain manufacturing steps – notably optical exposure, resist development and etch, chemical vapor deposition and chemical-mechanical polishing (CM...
ICC
2009
IEEE
14 years 4 months ago
2009
IEEE
—Physical-layer network coding (PLNC) is a novel wireless communication technology, in which multiple transmitters can send signals on the same channel to the same receiver at th...
ICCAD
2008
IEEE
14 years 6 months ago
2008
IEEE
Abstract— As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasing...
DAC
2000
ACM
14 years 10 months ago
2000
ACM
Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. Semiconductor Industry Association (SIA) roadmap predicts that, beyond the ...
ASPDAC
2008
ACM
13 years 11 months ago
2008
ACM
Continuous transistor scaling due to improvements in CMOS devices and manufacturing technologies is increasing processor power densities and temperatures; thus, creating challenges...