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» Lazy Error Detection for Microprocessor Functional Units
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DATE
2010
IEEE
148views Hardware» more  DATE 2010»
14 years 16 days ago
Scalable stochastic processors
Abstract—Future microprocessors increasingly rely on an unreliable CMOS fabric due to aggressive scaling of voltage and frequency, and shrinking design margins. Fortunately, many...
Sriram Narayanan, John Sartori, Rakesh Kumar, Doug...
ISCA
2002
IEEE
102views Hardware» more  ISCA 2002»
14 years 11 days ago
Implementing Optimizations at Decode Time
The number of pipeline stages separating dynamic instruction scheduling from instruction execution has increased considerably in recent out-of-order microprocessor implementations...
Ilhyun Kim, Mikko H. Lipasti
SIGSOFT
2010
ACM
13 years 5 months ago
Scalable SMT-based verification of GPU kernel functions
Interest in Graphical Processing Units (GPUs) is skyrocketing due to their potential to yield spectacular performance on many important computing applications. Unfortunately, writ...
Guodong Li, Ganesh Gopalakrishnan
MTV
2007
IEEE
121views Hardware» more  MTV 2007»
14 years 1 months ago
Chico: An On-chip Hardware Checker for Pipeline Control Logic
The widening gap between CPU complexity and verification capability is becoming increasingly more salient. It is impossible to completely verify the functionality of a modern mic...
Andrew DeOrio, Adam Bauserman, Valeria Bertacco
IV
2008
IEEE
105views Visualization» more  IV 2008»
14 years 1 months ago
A Dual-View Visualization of In-Car Communication Processes
With the increasing complexity of in-car communication architectures, their diagnostics have become essential for automotive development and maintenance. In order to help engineer...
Michael Sedlmair, Wolfgang Hintermaier, Konrad Sto...