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» Leakage Current Reduction in VLSI Systems
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DAC
2006
ACM
14 years 9 months ago
A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates
Substantial increase in leakage current and threshold voltage fluctuations are making design of robust wide fan-in dynamic gates a challenging task. Traditionally, a PMOS keeper t...
Hamed F. Dadgour, Rajiv V. Joshi, Kaustav Banerjee
GLVLSI
2009
IEEE
158views VLSI» more  GLVLSI 2009»
14 years 20 days ago
Exploration of memory hierarchy configurations for efficient garbage collection on high-performance embedded systems
Modern embedded devices (e.g., PDAs, mobile phones) are now incorporating Java as a very popular implementation language in their designs. These new embedded systems include multi...
José Manuel Velasco, David Atienza, Katzali...
ISLPED
2009
ACM
168views Hardware» more  ISLPED 2009»
14 years 3 months ago
Low power circuit design based on heterojunction tunneling transistors (HETTs)
The theoretical lower limit of subthreshold swing in MOSFETs (60 mV/decade) significantly restricts low voltage operation since it results in a low ON to OFF current ratio at low ...
Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, ...
DAC
1998
ACM
14 years 9 months ago
A Mixed Nodal-Mesh Formulation for Efficient Extraction and Passive Reduced-Order Modeling of 3D Interconnects
As VLSI circuit speeds have increased, reliable chip and system design can no longer be performed without accurate threedimensional interconnect models. In this paper, we describe...
Nuno Alexandre Marques, Mattan Kamon, Jacob White,...
VLSID
1994
IEEE
84views VLSI» more  VLSID 1994»
14 years 27 days ago
Energy Efficient Programmable Computation
: This paper describes techniques for energy efficient implementation of programmable computation. consumption in programmable computation can be substantiallvlowered with nolossin...
Anantha Chandrakasan, Mani B. Srivastava, Robert W...